• 专利附录
  • 专利说明
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    • 专利摘要:
    The invention relates to an electronic chip comprising an integrated circuit (1) arranged on one side of the front face (4) or the rear face (5) of a substrate (2) and a protection device (3) arranged at least partially with regard to the integrated circuit (1) characterized in that the protection device comprises at least one capacitor comprising a first electrode (6) and a second electrode (7) between which is disposed at least one layer of phase change material (8) configured to pass at least locally from a first resistive state to a second resistive state different from the first state by penetration of a photon and / or ion beam (9), the first state being an amorphous state for which the capacitor has a first capacitance and / or a first resistance and the second state is a crystalline state for which the capacitor has a second capacitance and / or a second resistance respectively different from the first capacitance and the first resistance, the protection device being electrically connected to the integrated circuit (1) by at least one of said first or second electrodes (6-7) so that the integrated circuit (1) measures the resistance and / or capacitance of the capacitor. The invention will find application in the field of security and protection of electronic chips. The invention applies to any type of electronic chip: mobile phone chip, bank card, microprocessor health card, interposer (for example of central computer), microcontroller etc ...
    公开号:FR3031836A1
    申请号:FR1550329
    申请日:2015-01-15
    公开日:2016-07-22
    发明作者:Yann Lamy；Luca Perniola
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention relates to an electronic chip provided with a protection device with a phase change material, a method for detecting an attack of the chip and a method of manufacturing said chip.
    [0002] The invention will find application in the field of security and protection of electronic chips. The invention applies to any type of electronic chip: mobile phone chip, bank card, health card, microprocessor, interposer (for example central computer), microcontroller etc ...
    [0003] STATE OF THE ART The attacks that an electronic chip may undergo are intended to access confidential data stored in the electronic chip, in particular to clone it, or modify the stored information. The electronic chips can be attacked in various ways: chemical, physical, laser, electromagnetic, electric ... These attacks are generally implemented by following two objectives. The first is to acquire or retrieve internal information manipulated by the integrated circuit of the chip (observation of the electrical consumption of the circuit, the electromagnetic radiation produced by the circuit, "probing" of the circuit, that is to say physically access to the circuit by establishing an electrical connection with an internal track of the circuit, "probing" without contact of an internal track, etc.). The second consists in injecting faults (change of state of a bit or a group of bits via an injection of light, of laser, of electromagnetic radiation, etc.) during a computation carried out by the integrated circuit of the chip. Very often, a combination of these different techniques is used. To guard against such attacks, there are several types of protections. The first level of protection is the physical physical protection of the chips. The front face of an electronic chip (on the face of which the integrated circuit of the chip is conventionally located) can for example be protected by adding special protective layers on this front face. There are also protections on the back of the chip. Indeed, the rear face of the chip is a sensitive area that can be attacked with current etching and thinning techniques to approach a very short distance from the integrated circuit of the chip to recover stored information or inject faults in the chip. Moreover, to be effective, it is necessary to be able to check the integrity of the protection device and detect an attack.
    [0004] However, the solutions proposed to date do not provide both effective protection without risk of tampering or removal of the protective device and reliably detect the integrity of said protection. There is therefore the need to provide an electronic chip whose integrated circuit is effectively protected and that the largest number of attacks is reliably detected. SUMMARY OF THE INVENTION The present invention proposes for this purpose an electronic chip comprising an integrated circuit disposed on one face of the front face or the rear face of a substrate and a protection device arranged at least partially opposite the integrated circuit. The protection device comprises at least one capacitor comprising a first electrode and a second electrode and at least one layer of phase change material interposed between said two electrodes. The at least one layer of phase change material is configured to pass at least locally from a first resistive state to a second resistive state different from the first state by penetration of a photon and / or ion beam. The first resistive state is selected from an amorphous state for which the capacitor has a first resistance and / or a first capacitance and a crystalline state for which the capacitor has a second resistor and / or a second capacitance. The second resistance and the second capacitance are respectively different from the first capacitance and the first resistance. . The protection device is electrically connected to the integrated circuit so that the integrated circuit detects the resistance or capacitance of the capacitor. This detection thus makes it possible to identify a change of state of the at least one layer of MCP and thus detect an attack of the electronic chip. The invention combines reliable protection of the integrated circuit with a protective stack comprising a plurality of layers and reliable detection of any attack by the change of state of a phase change material contained in a capacitor. Phase change materials are materials in which a resistive transition can be observed. The phase change material is configured to alternatively take a highly resistive state, also referred to as a high resistance state, HRS for High Resistive State in English, and a low resistive state also referred to as a low resistance state, LRS for Low Resistive State. The phase change material is said to be in a highly resistive state, HRS, when its resistance is greater than that of the material in a weakly resistive state LRS. Conventionally, an amorphous state is an HRS state and a crystalline state is an LRS state. A phase change material and the two electrodes in which the phase change material is interposed form a capacitor whose capacitive and resistive properties vary according to the state of the phase change material. The presence of a capacitor arranged at least partially opposite the integrated circuit, advantageously on one of the faces of the electronic chip, has a physical protection of the chip by increasing the thickness to access the integrated circuit whether by its front face or by its back side. Furthermore, a capacitor according to the invention comprising a phase change material layer provides protection against laser attacks. Indeed, an ionic and / or photonic beam will act on the phase change material and cause its change of state advantageously by changing it from an HRS state to LRS. This change of state is detected by the integrated circuit to which the protection device is connected. Preferably, this detection causes the default of the integrated circuit. According to a preferred embodiment, the protection device is disposed on a face opposite to the integrated circuit, preferably on the rear face, the sensitive face of the electronic chip.
    [0005] It is advantageous that the capacitor comprises at least three layers of stacked phase change materials. Indeed, under the effect of a photon beam and / or ion, the heat received by the inner layer will be confined by two other outer layers located on either side of the inner layer. This confinement of the heat allows a rapid rise in temperature in the layer of material with internal phase change, thus promoting a rapid change of state. The presence of three stacked layers makes it possible to maintain at least one layer of phase-change material in a confined HRS state providing finer detection of photon and / or ion beam etching.
    [0006] BRIEF DESCRIPTION OF THE FIGURES The objects, objects, as well as the features and advantages of the invention will emerge more clearly from the detailed description of an embodiment of the latter which is illustrated by the accompanying figures in which: Figure 1: Architecture a capacitor according to an embodiment for a protection device according to the invention.
    [0007] Figure 2: Schematic view of an electronic chip according to the invention comprising an integrated circuit on the front face and a protective device on the rear face subjected to a laser attack. Figure 3: Diagrammatic view of an electronic chip according to the invention comprising an integrated circuit on the front face and a protection device on the rear face subjected to a focused ion beam (FI B Focus ion beam in English). Figure 4: View of a protection device according to another embodiment arranged on a face of a substrate and subjected to a laser beam. Figure 5: View of a protection device according to another embodiment arranged on a face of a substrate comprising a plurality of capacitors. Figure 6: Mapping of the absorption coefficient of the photon radiation of the stack of a capacitor of the protection device according to the thickness of the outer layers of phase change material. Figure 7: Evolution of the maximum temperature in the stack as a function of time during a laser pulse of 3Ons and for the next 3Ons. Figure 8: Temperature profile in the thickness of the capacitor at the end of a laser irradiation of 3Ons, exactly at t = 3Ons. The accompanying drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications. In particular, the relative thicknesses of the different layers and films are not representative of reality.
    [0008] DETAILED DESCRIPTION OF THE INVENTION Before beginning a detailed review of embodiments of the invention, it is first recalled that the invention relates to a first aspect of an electronic chip comprising an integrated circuit arranged on one side of the front face or the rear face of a substrate and a protection device arranged at least partially with respect to the integrated circuit characterized in that the protection device comprises at least one capacitor comprising a first electrode and a second electrode between which is disposed at least one layer of phase change material configured to pass at least locally from a first resistive state to a second resistive state different from the first state by penetration of a photonic and / or ionic beam, the first state being an amorphous state for which the capacitor has a first capacitance and / or a first resistance and the second capacitor at being a crystalline state for which the capacitor has a second capacitance and / or a second resistance respectively different from the first capacitance and the first resistance, the protection device being electrically connected to the integrated circuit by at least one of said first or second electrodes so that the integrated circuit measures the resistance and / or capacitance of the capacitor. The following are optional features that can optionally be used in combination or alternatively: the second resistance of the capacitor is lower than the first resistance; - The protection device is arranged on a second face of the substrate, different from the first face on which the integrated circuit is arranged and selected from the front face or the rear face of the substrate; the protection device comprises at least three stacked layers of phase-change materials defining two outer layers and at least one inner layer; the two outer layers are in a crystalline state and the at least one inner layer is in an amorphous state; the crystallization temperature of the at least one inner layer of phase change material is greater than the crystallization temperatures of the outer layers of phase change material; the outer layers of phase-change material have a thickness of between 50 nm and 200 nm; the at least one inner layer of phase change material has a thickness of between 5 and 30 nm; The protection circuit is electrically connected to the integrated circuit by a buried interconnection; the protection device extends over a surface of the substrate at least equivalent to the surface on which the integrated circuit extends; the at least one capacitor comprises at least one trench formed in the thickness of the substrate; the trench is of a width of 500 nm to 1 μm; the protection device comprises a plurality of capacitors connected in series. According to another aspect, the invention also relates to a method for detecting an attack by an ionic and / or photonic beam of the electronic chip as described above, characterized in that it comprises the following steps performed by the integrated circuit: - identification of the capacity and / or the so-called initial resistance of the protection device; - subsequent measurement of the capacity and / or the subsequent resistance of the protective device; - comparison of the capacity and / or the subsequent resistance with the initial capacity and / or resistance, identical values indicating the absence of attack of the electronic chip, different values indicating the existence of an attack of the electronic chip having led to the change of state of at least one layer of material with state change. Advantageously, the identification of the initial capacity and / or initial resistance is carried out by measuring the initial capacity and / or initial resistance of the protection device. According to another aspect, the invention relates to a method for manufacturing an electronic chip as described above characterized in that it comprises at least the following steps of: - formation of an integrated circuit at a level of face of a substrate chosen from the front face or the rear face; forming at least one capacitor at least partially with respect to the integrated circuit comprising depositing a first electrode, depositing at least one layer of phase change material configured to pass at least locally from a first state at a second state different from the first state by penetration of a photonic and / or ionic beam, the first state being an amorphous state for which the capacitor has a first capacitance and / or a first resistance and the second state being a crystalline state for wherein the capacitor has a second capacitance and / or second resistance respectively different from the first capacitance and the first resistance, and depositing a second electrode; - electrical connection of the protection circuit to the integrated circuit. Advantageously, the deposition of at least one layer of phase change material comprises the deposition of at least three layers of stacked phase change material defining two outer layers and at least one inner layer.
    [0009] Advantageously, the steps subsequent to the deposition of the at least one inner layer are configured so as to maintain the first state of the at least one inner layer of phase change material. Advantageously, the manufacturing method comprises a step subsequent to the deposition of at least one inner layer configured to pass the phase-change material of at least one of the two outer layers of a first state to a second different state. of the first state. It is specified that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or another element.
    [0010] It is established that the capacitance of a capacitor is essentially determined by the geometry of the electrodes and the nature of the insulator (s); the following simplified formula is often used to estimate its value: C = E-e Formula I With S: surface of the electrodes opposite, e: distance between the electrodes and E the permittivity of the dielectric. In the context of the present invention, the dielectric is the phase change material (PCM) whose resistance depends on its state. The electronic chip according to the invention comprises a substrate 2 on which, preferentially on its front face 4, is arranged an electronic circuit preferably an integrated circuit 1. The integrated circuit 1 may be various, for example a semiconductor complementary to the Metal Oxide (CMOS: Complementary Metal Oxide Semiconductor) can be used. The substrate 2 may comprise several integrated circuits 1 protected or not by the same or more protection device 3 described below.
    [0011] According to the invention, the electronic chip comprises a protection device 3 arranged at least partially facing the integrated circuit 1, advantageously on one of the front or rear faces of the substrate 2. In the case of an arrangement on the front face, the device protection device can be formed directly above the integrated circuit 1. The protection device can also be buried in the substrate, or be formed on another substrate arranged at least partially facing the integrated circuit 1, such as for example a hood of protection of the integrated circuit 1. The protection device 3 is arranged at least partially opposite the integrated circuit 1 and, advantageously to ensure optimum protection, the protection device 3 extends over a surface of the substrate 2 greater than the surface of the integrated circuit 1 as illustrated in FIG.
    [0012] According to a preferred embodiment, the protection device 3 is placed on the face of the substrate 2 opposite to the face receiving the integrated circuit 1. Preferably, the protection device 3 is on the rear face 5 and the integrated circuit 1 is opposite. before 4 of the substrate 2. The protection device 3 comprises a capacitor. The capacitor comprises a first electrode 6, also called "top electrode" for upper electrode and a second electrode 7, also called "bottom electrode" for lower electrode. The capacitor comprises between the first electrode 6 and the second electrode 7, at least one layer of MCP 8. The capacitor is a stack of layers comprising at least the two electrodes 6, 7 and at least one layer MCP 8 interposed. The protection device 3 is electrically connected to the integrated circuit 1, preferably by at least one of the two electrodes 6, 7. According to one possibility, the protection device 3 is connected by an electrode 6, 7 to the integrated circuit 1 and is connected to a reference mass by the other of said electrodes, 6, 7. This mass may be external to the integrated circuit 1. According to another preferred possibility, the two electrodes 6, 7 are electrically connected to the integrated circuit 1. In the case where the device protection 3 is arranged on the same side as the integrated circuit 1 the electrical connections are standard microelectronic connections composed of horizontal conductive lines (eg copper) and vertical connections (vias in English). In the case where the protection device 3 is arranged on a face opposite to the integrated circuit 1, the electrical connections are vertical interconnections also said buried through the substrate 2, for example by trenches through the silicon (Through Silicon Vias - TVS in English). The electrical connection of the capacitor directly to the integrated circuit 1 allows a measurement of capacitance and / or resistance of the capacitor and thus allows the detection of an attack by ionic and / or photonic beam 9. Thanks to the invention , the integrated circuit 1 advantageously continuously measures the capacitance and / or resistance of the capacitor, which implies that the control of the state of the MCP is continuous and therefore the detection of an attack is permanent.
    [0013] The following description is made for a capacitor of the protection device 3. The protection device may comprise several capacitors as described below and illustrated in FIG. 5.
    [0014] The capacitor according to the invention comprises at least one layer of MCP 8. The MCP 8 is preferably in a first state before any photon and / or ion beam etching. The penetration of a photonic and / or ionic beam 9 through the at least one layer of MCP 8 causes the change of state of said MCP 8 to a second state. The first state and the second state are different states and advantageously, the first state and the second state have different resistances. The different resistance of the MCP 8 between the first state and the second state also implies capacitance and / or resistance different from the capacitor depending on the state of the MCP 8.
    [0015] The first state and the second state are selected from a highly resistive state, also referred to as high resistance state, HRS for High Resistive State in English, and a weakly resistive state also referred to as low resistance state, LRS for Low Resistive State in English. The phase change material is said to be in a highly resistive state, HRS, when its resistance is greater than that of the material in a weakly resistive state LRS. Preferably, the highly resistive state or HRS is also referred to as the amorphous state and the weakly resistive state or LRS is also referred to as the crystalline state. According to a preferred embodiment, the first state of the at least one layer of MCP 8 is a highly resistive state HRS, amorphous state for which the capacitor has a first capacitance and / or a first resistance and the second state is a weakly state. resistive LRS, crystalline state, for which the capacitor has a second capacitance and / or a second resistance. In this way, the change of state of the MCP 8 involves a change of resistance and / or capacity of the capacitor which is detected by the integrated circuit 1. Advantageously, the second resistance of the capacitor is lower than the first resistor of the capacitor. The first capacity of the capacitor is constant for the first state of the at least one layer of MCP 8. The second capacity of the capacitor is variable for the second state of the at least one MCP layer 8 in particular as a function of the partial state change or total of the at least one layer of MCP 8 and the number of layers of MCP 8. The second capacity may be less than or greater than the first capacity. The integrated circuit 1 electrically connected to the capacitor can monitor a change in capacitance and / or resistance of said capacitor. The penetration of the ionic and / or photonic beam 9 into the at least one layer of MCP 8 results in an at least local increase in temperature. It is this temperature increase that will trigger the transition from the first state to the second MCP state.
    [0016] Photonic and / or ionic beam 9 is understood to mean a laser beam or ion beam known as FIB (Focus Ion Beam). The laser-type photonic beams conventionally used for the attacks of electronic chips have a wavelength of 40nm to 1500nm. The ion beam attack, FIB, although considered a destructive attack of the electronic chip, can be extremely localized with holes of a few microns. This localized destruction involves only a small modification of the electronic chip which is not easily identifiable. However, the protection device 3 according to the invention is also sensitive to this type of attack which generates a heating 14 at the level of the destruction zone, as illustrated in FIG. 3. This localized heating 14 causes a change of state of the MCP layer 8 of the capacitor of the protection device 3. The transition to the crystallized state of at least one layer of MCP 8 locally at the level of the walls of the destruction zone causes a change in the capacitance and / or the resistance of the capacitor which is detected by the integrated circuit 1.
    [0017] The transition from the first state to the second state of the MCP may be only local in the MCP layer 8. That is, it is not necessary for the entire MCP layer 8 to go from the first state to the next state. second state. Advantageously, a local change sufficient to involve a change in the resistance of the MCP and therefore the capacitance and / or resistance of the capacitor which is detected by the integrated circuit 1. Preferably, the capacitor comprises three layers of MCP stacked between the two 6, 7. This arrangement makes it possible to propose a protection device 3 that is more sensitive to the photonic and / or ionic beam 9. The stack defines two layers of external MCP 10a, 10b. Between the two outer layers 10a, 10b, the stack comprises an inner layer 11 of MCP. The two outer layers 10a, 10b have a heat concentration action during the ionic and / or photonic beam etching 9 very significantly promoting the rise of the temperature in the inner layer 11. The transition from the first state to the second state is accelerated for the inner layer allowing detection even in case of short-term attack. In order to obtain optimal ion and / or photon beam etch detection, it is preferred that the capacitor comprises multiple layers of MCP. The stacking of three layers of MCP is a preferred embodiment. The outer layers 10a 10b are respectively in contact with the first electrode 6 and the second electrode 7. Advantageously, the inner layer 11 is in a first state, HRS, amorphous. This inner layer 11 is thus buried in the stack of layers of MCP 8. The two outer layers 10a, 10b are preferably in a second state, LRS, crystalline. In this way, these two outer layers 10a, 10b act as a buffer against the dissipation of heat from the inner layer 11. The two outer layers 10a, 10b in their crystalline state play a role of thermal insulation of the layer internal 11, without limiting the detection threshold of the attack ion beam or photon 9. The heat received by the inner layer 11 during the attack is maintained therein. According to a preferred embodiment, the inner layer 11, or the at least one layer of MCP 8 in the case of a single layer of MCP 8 in the capacitor, is in a first state said original state. Preferably, the first state is the HRS state, amorphous. The term "original" means the state obtained at the end of the deposition step of said layer and before any further manufacturing or programming step or state change. In the original state, the value of the capacitance and / or the resistance is called initial. In the case of the stack of three layers of MCP, it is preferred that the crystallization temperature of the MCP of the inner layer 11 is greater than the crystallization temperature of the MCP or the outer layers 10a, 10b. Formulated differently, it is preferred that the thermal budget of the manufacturing steps of the electronic chip after the deposition step of the inner layer 11 is less than the crystallization temperature of the MCP of the inner layer 11. The inner layer 11 has preferably a thickness of between 5 and 30 nm, preferably 10 nm. The thickness of the inner layer 11 is defined to be sufficiently thick to provide electrical insulation in its amorphous state and sufficiently thin to allow the formation of a conductive path when moving to a crystalline state. The outer layers 10a, 10b have a thickness sufficient to prevent rapid cooling of the inner layer 11 in contact may cause unexpected changes in state of MCP from a crystalline state to an amorphous state. For example, a thickness of less than or equal to 200 nm is preferred. Moreover, the thickness of the inner layers 10a, 10b must be sufficient to act as a thermal insulator between the inner layer 11 and the electrodes 6, 7. For example, the thickness is greater than or equal to 50 nm. The MCP that can be used to form the at least one layer of MCP 8 is GST: GexSbyTe. This type of MCP is particularly sensitive to the heating generated by an ion beam and / or photon. It can be easily deposited by vapor deposition (PVD for Physical Vapor Deposition) or plasma-enhanced chemical vapor deposition (PECVD) for plasma at various temperatures, which is very useful for manufacturing method of the invention described hereinafter.
    [0018] To adjust the thermal conductivity Kth, the specific heat volume Cv or the crystallization temperature, dopants may be introduced into the MCP such as oxygen, nitrogen, indium, cerium. The doping of the MCP influences in particular the crystallization temperature. For example, the crystallization temperature of the carbon-doped GeTe varies from 170 ° C. for 0% of carbon to more than 400 ° C. for 24% of carbon. In the case of carbon-doped GST, the crystallization temperature varies from 150 ° C. for 0% of carbon to more than 340 ° C. for 24% of carbon. In the case of GeTe doped with nitrogen, the crystallization temperature varies from 170 ° C. for 0% of nitrogen to more than 270 ° C. for 10% of nitrogen. These variations in crystallization temperature are not followed by the same variations in the melting temperature. For example, GeTe and GeTe doped with 10% nitrogen has substantially the same melting temperature around 715 ° C. According to one aspect, the invention relates to a method of manufacturing an electronic chip as described, more specifically to the method of manufacturing the protection device on an electronic chip provided on one side with at least one integrated circuit. substrate at least one integrated circuit 1 is first formed. The process comprises the following steps: deposition, for example by vapor deposition (PVD for Physical Vapor Deposition) of the second electrode 7, for example aluminum, indium tin oxide transparent electrode (ITO for Indium Tin Oxide) . Depositing at least one layer of MCP 8, for example successive deposition of three layers, two of which are external 10a, 10b, and one internal, 11, for example by vapor deposition (PVD for Physical Vapor Deposition) or by chemical deposition; Plasma Enhanced Chemical Vapor Deposition (PECVD). Deposition of the first electrode 6, for example made of aluminum, transparent indium tin oxide (ITO for Indium Tin Oxide) electrode, for example by vapor deposition (PVD for Physical Vapor Deposit) or by chemical vapor deposition Plasma-Enhanced Chemical Vapor Deposition (PECVD). By way of example, the first electrode 6 and the second electrode 7 are made of aluminum with a respective thickness of 50 nm and the inner layer 11 is 10 nm thick. The deposition step of the first electrode 6 is carried out at a temperature below the crystallization temperature of the at least one layer of MCP 8, more precisely lower than the crystallization temperature of the MCP of the inner layer 11.
    [0019] According to one embodiment, the method comprises a step of annealing after the deposition of the at least three layers of MCP 10a, 10b, 11. This annealing step is carried out at a temperature greater than the crystallization temperature of the MCP or layers external 10a, 10b but at a temperature below the crystallization temperature of the MCP of the inner layer 11. In this way, the outer layers 10a, 10b will be in a state of crystallization while the inner layer 11 will remain in an original state , preferably an amorphous state. It is advantageous for the properties of the protection device and more specifically of the capacitor to be optimized so as to obtain a probability of detection of any highest possible ionic and / or photon beam attack. The non-exhaustive parameters involved in the optimization of the capacitor are on the one hand the parameters of the materials of each layer of the stack forming the capacitor including the electrodes 6, 7: for example the refractive index n, the index d absorption k, the thermal conductivity Kth, the specific heat volume Cv, the thickness t. The value of these parameters are intrinsic to the chosen materials and are known for each one in the literature and, on the other hand, the properties of the photonic and / or ionic beam 9 used to attack the electronic chip: wavelength λ, power Pw, the size of the beam at the point of contact d, the duration of the laser pulsation tpulse, the duration between each pulse t -idle- From such information, the absorbance of the MPC layers can be maximized and therefore also the thermal profile at inside the capacitor during laser firing. In order to ensure that a crystalline percolation path is created within the inner layer 11 of MPC, the temperature must rise locally above the crystallization temperature of the inner layer 11 of MCP, so that crystallization is triggered. Example: An example of quantitative optimization of the capacitor illustrated in Figure 1 is performed as follows. In the following microscopic parameters (when not defined elsewhere) are those of the GST (germanium alloy, antimony and tellurium in a proportion 225, Ge2Sb2Te5). The outer layers of MCP 10a, 10b consist of standard GST having a crystallization temperature Tc of the order of 150 ° C, to find them in the crystalline state at the end of the manufacturing process. The inner layer of MCP consists of a doped carbon version of GST, more precisely GST-C15%, which makes it possible to increase the temperature of crystallization Tc - 150 ° C from GST to Tc - 325 ° C for GST-C15 %, without substantially modifying the other parameters such as the refractive index n (= 3.8) and the absorption index k (= 3.4), in order to ensure its amorphous integrity at the end of the process of manufacturing. The thermal conductivity Kth and the specific heat volume Cv are identical for the MCP of the inner 11 and outer layers 10a, 10b in the amorphous state and in the crystalline state (Kth = 0.3 VV / m * K; Cv = 1.3e6 J / m3 * K).
    [0020] The steps to optimize the stacking are described below: 1. Maximize the absorption of the stack in order to convert as quickly as possible any attack by ion beam and / or photon 9 in a thermal heating, in order to cause crystallization at least one layer of MCP 8, more precisely of the inner layer 11 of MCP. From n, k, Ke, λ = 1000 nm (wavelength generally used for the attacks), calculate the dimensions of the outer layers 10a, 10b, in particular the thickness in order to have maximum absorbance. In Figure 6, a local maximum is obtained for the outer layer 10a = 200 nm and the outer layer 10b 200 nm. (Internal layer 11 = 10 nm is constant). These are not the only possibilities, since from the map of FIG. 6, other maxima can be deduced which can also be used, for example external layer 10a = 400 nm and external layer 10b = 200 nm. (Internal layer 11 = 10 nm is constant). It is preferable to avoid the maxima that fall t = 0 nm for the other layer which would imply poor thermal insulation vis-à-vis the electrodes 6, 7 and therefore a decrease in the reliability of the detection of attacks. 2. Calculate the distribution of the temperature inside the stack with all the parameters concerning the materials and the laser with d = 2 μm, Pw = 250 mVV, Tpuise = 30 ns, Tidie = 30 ns, we obtain the 7 and 8. In order to be sure that the laser attack is detected, the inner layer 11 in the amorphous state must crystallize. It is therefore necessary that the temperature inside the inner layer 11 is greater than the crystallization temperature of the MCP of this layer. If for example the internal Tc-layer 11 - 400 ° C, the crystallization begins after 10 ns of laser pulsation. We also note that it is impossible to have a crystalline to parasitic amorphous transition in said inner layer 11 during the intermediate phases (denoted "recovery" in FIG. 7) between the laser pulsations, because the cooling rate of the MCP is very slow compared to the speed necessary for the transition to the amorphous state, usually greater than 1e10 K / sec). According to possible variants, the capacitor has a 3D structure. Trenches 12 are formed in the substrate 2. The trenches 12 are made by conventional etching techniques. The stack of the capacitor is then deposited in the trenches 12. Each trench 12 receives the second electrode 7, the at least one layer of MCP 8 and the first electrode 6. Preferably, the at least one layer of MCP 8 fills the trench and restore a plane on which is deposited the first electrode 6. Such a structure is illustrated in Figure 4 with three layers of MCP 10a, 10b, 11. Preferably, a trench has a width dimension of 500nm to lpm. In this way, a conventional laser beam with a contact point diameter of the order of 1 to 2 μm will affect at least one trench 12. This trench structure of the capacitor of the protection device 3 increases the volume of MCP passed through the trench. amorphous state of the inner layer 11 and MCP of the outer layers 10a, 10b which receives the ion beam and / or photon 9. The heat generated in the MCP is therefore increased defining an increased sensitivity to the protection device 3 even for attacks at low power. According to another possibility, the protection device 3 comprises a plurality of capacitors in series. To obtain this structure, several capacitors as described above are arranged on one side of the substrate 2 and are connected in series. An exemplary structure is illustrated in FIG. 5. Islands of insulation 15 are deposited between the capacitors so as to ensure a series connection. In Figure 5, the capacitors are identical, however, there may be provided a protection device with different capacitors. According to this possibility, it is the capacity and / or the total resistance of the protection device 3 which is monitored. The inverse of the total capacity is calculated by the following formula where C1 corresponds to the capacity of the first structure C2, ... CN the capacities of the second or nth structure 1 / Ctotal = e_1 (1 / C1) When of an attack by ionic and / or photonic beam 9, it suffices that an inner layer 11 of MCP goes to the crystalline state to change the capacity and / or the total resistance of the protection device 3 with respect to its initial state. This modification of the capacitance and / or the total resistance is detected by the integrated circuit 1. According to one possibility, the inner layer of MCP 11 of certain capacitors connected in series can be in the crystalline state. Hereinafter, a photon and / or ionic etching process detection method 9 of an electronic chip as described above is described. Each protection device 3 has a so-called reference capacity (RCV for Reference Capacitance Value) or RRV (for Reference Resistance Value). Below we will take the example of the RCV, but it can be transposed in the same way for the RRV. This RRS must be maintained throughout the life of the microchip. A change of value of the capacitance must be detected by the integrated circuit 1 as the signal of an attack.
    [0021] Preferably, the integrated circuit 1 itself identifies the RCV which must be maintained throughout the life of the electronic chip. This RCV corresponds to the initial capacity of the protection device 3. It is advantageously measured at the commissioning of the electronic chip. According to another embodiment, the RCV is a piece of data written in the electronic chip during its manufacture. The integrated circuit 1 retrieves this data during the commissioning of the electronic chip. It is preferred to measure initial capacity rather than having an initial coding since this avoids an attack for the recovery of this RCV data or its imposition to foil detection of the attack.
    [0022] During the life of the electronic chip, the integrated circuit 1 makes subsequent measurements of the capacitance of the protection device 3. The electronic chip compares the subsequent value of the capacitance with the initial capacitance RCV. The identification of a difference signals the existence of an attack by photonic and / or ion beam 9. Advantageously, the microchip immediately goes into default so as to prevent the success of the attack and make it possible to inform the user. user of the existence of an attack.
    [0023] REFERENCES 1. Integrated circuit 2. Substrate 3. Protection device 4. Front face of the substrate 5. Rear face of the substrate 6. First electrode 7. Second electrode 8. Phase change material layer 9. Ionic and / or photonic beam 10a . External layer of phase change material 10b. External layer of phase change material 11. Internal layer of phase change material 12. Trenches 13. Electrical connection 14. Heating 15. Insulation20
    权利要求:
    Claims (14)
    [0001]
    CLAIMS1 An electronic chip comprising an integrated circuit (1) arranged on one face of the front face (4) or the rear face (5) of a substrate (2) and a protection device (3) arranged at least partially with respect to the integrated circuit (1) characterized in that the protection device comprises at least one capacitor comprising a first electrode (6) and a second electrode (7) between which is disposed at least one layer of phase change material (8) configured to pass at least locally from a first resistive state to a second resistive state different from the first state by penetration of a photonic and / or ionic beam (9), the first state being an amorphous state for which the capacitor has a first capacitance and / or a first resistance and the second state being a crystalline state for which the capacitor has a second capacitance and / or a second resistance respectively dif of the first capacitance and the first resistance, the protection device being electrically connected to the integrated circuit (1) by at least one of said first or second electrodes (6-7) so that the integrated circuit (1) measures the resistance and / or capacitance of the capacitor.
    [0002]
    2. The chip of claim 1 wherein the second resistor of the capacitor is less than the first resistor.
    [0003]
    3. A chip according to any preceding claim wherein the protection device (3) is arranged on a second face of the substrate (2), different from the first face on which the integrated circuit (1) is arranged and selected from the front face (4) or the rear face (5) of the substrate (2).
    [0004]
    A chip according to any one of the preceding claims wherein the protection device (3) comprises at least three stacked layers of phase change materials defining two outer layers (10a, 10b) and at least one inner layer (11). .
    [0005]
    5. Chip according to the preceding claim wherein the two outer layers (10a, 10b) are in a crystalline state and the at least one inner layer (11) is in an amorphous state.
    [0006]
    6. A chip according to any one of the two preceding claims wherein the crystallization temperature of the at least one inner layer (11) of phase change material is greater than the crystallization temperatures of the outer layers (10a, 10b) of material to phase change.
    [0007]
    A chip according to any one of the three preceding claims wherein the outer layers (10a, 10b) of phase change material have a thickness of between 50nm and 200nm.
    [0008]
    8. A chip according to any of the four preceding claims wherein the at least one inner layer (11) of phase change material has a thickness between 5 and 30nm.
    [0009]
    9. A chip according to any one of the preceding claims wherein the protection circuit (3) is electrically connected to the integrated circuit (1) by a buried interconnection.
    [0010]
    10. A chip according to any one of the preceding claims wherein the protection device (3) extends over a surface of the substrate (2) at least equivalent to the surface on which the integrated circuit (1) extends.
    [0011]
    11. A chip according to any one of the preceding claims wherein the at least one capacitor comprises at least one trench (12) formed in the thickness of the substrate (2).
    [0012]
    12. Chip according to the preceding claim wherein the trench (12) has a width of 500nm to lpm.
    [0013]
    A chip according to any one of the preceding claims wherein the protection device (3) comprises a plurality of capacitors connected in series.
    [0014]
    14. A method for detecting an attack by an ionic and / or photonic beam (9) of the electronic chip according to any one of the preceding claims, characterized in that it comprises the following steps performed by the integrated circuit (1). : - identification of the capacity and / or the so-called initial resistance of the protection device (3); - subsequent measurement of the capacity and / or the subsequent resistance of the protective device (3); - comparison of the capacity and / or the subsequent resistance with the initial capacity and / or resistance, identical values indicating the absence of attack of the electronic chip, different values indicating the existence of an attack of the electronic chip having led to the change of state of at least one layer of state change material (8). Detection method according to the preceding claim wherein the identification of the initial capacity and / or initial resistance is performed by measuring the initial capacity and / or initial resistance of the protection device (3). 16. A method of manufacturing an electronic chip according to any one of claims 1 to 13 characterized in that it comprises at least the following steps of: - forming an integrated circuit (1) at a face a substrate (2) selected from the front face (4) or the rear face (5); forming at least one capacitor at least partially with respect to the integrated circuit (1) comprising depositing a first electrode (6), depositing at least one layer of phase-change material (8) configured to at least locally from a first state to a second state different from the first state by penetration of a photonic and / or ion beam (9), the first state being an amorphous state for which the capacitor has a first capacitance and / or a first resistor and the second state being a crystalline state for which the capacitor has a second capacitance and / or a second resistance respectively different from the first capacitance and the first resistance, and the deposition of a second electrode; - electrical connection (13) of the protection circuit (3) to the integrated circuit (1). 17. Manufacturing method according to the preceding claim wherein the deposition of at least one layer of phase change material (8) comprises the deposition of at least three layers of stacked phase change material defining two outer layers (10a). , 10b) and at least one inner layer (11). 18. Manufacturing method according to the preceding claim wherein the steps subsequent to the deposition of the at least one inner layer (11) are configured to maintain the first state of the at least one inner layer (11) of material change of phase. 19. Manufacturing method according to any one of the two preceding claims comprising a step subsequent to the deposition of at least one inner layer (11) configured to pass the phase change material of at least one of the two layers. external (10a, 10b) from a first state to a second state different from the first state.
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    同族专利:
    公开号 | 公开日
    EP3046147A3|2016-07-27|
    EP3046147A2|2016-07-20|
    FR3031836B1|2018-02-09|
    US9520366B2|2016-12-13|
    EP3046147B1|2019-12-25|
    US20160211230A1|2016-07-21|
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    法律状态:
    2016-01-28| PLFP| Fee payment|Year of fee payment: 2 |
    2016-07-22| PLSC| Publication of the preliminary search report|Effective date: 20160722 |
    2017-01-30| PLFP| Fee payment|Year of fee payment: 3 |
    2018-01-26| PLFP| Fee payment|Year of fee payment: 4 |
    2020-01-30| PLFP| Fee payment|Year of fee payment: 6 |
    2021-01-28| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1550329A|FR3031836B1|2015-01-15|2015-01-15|ELECTRONIC CHIP PROVIDED WITH A PHASE CHANGE MATERIAL PROTECTION DEVICE, A METHOD OF DETECTING A CHIP ATTACK, AND A METHOD OF MANUFACTURING THE CHIP.|
    FR1550329|2015-01-15|FR1550329A| FR3031836B1|2015-01-15|2015-01-15|ELECTRONIC CHIP PROVIDED WITH A PHASE CHANGE MATERIAL PROTECTION DEVICE, A METHOD OF DETECTING A CHIP ATTACK, AND A METHOD OF MANUFACTURING THE CHIP.|
    EP16151557.2A| EP3046147B1|2015-01-15|2016-01-15|Electronic chip provided with a protective device with phase change material, method for detecting an attack on the chip and method for manufacturing said chip|
    US14/996,566| US9520366B2|2015-01-15|2016-01-15|Chip comprising a phase change material based protecting device and a method of manufacturing the same|
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